Components and devices utilizing electrical circuits involving integrated circuit (IC) chips, multi-chip modules, printed circuit boards, connectors, back planes, and cards are generally referred to as electronic packaging. The terms “electronic packaging structure,” “electronic package,” and “package” are used interchangeably throughout this disclosure to generally refer to any and all of the aforementioned devices and structures. Also included in this definition is the specific case of multilayered packaging wherein multiple substantially parallel conducting ground and power planes are separated by dielectric substrates.
It is desirable and has long been the practice in this technology to employ simulation techniques to establish performance baselines of electronic packages prior to finalizing hardware design and prior to building prototype electronic packages in order to rapidly and inexpensively predict system behavior. While such simulations were simply useful when developing discrete and low density circuits, the preponderance of large scale integration (LSI), very large scale integration (VLSI), and ultra large scale integration (ULSI) implementations has made simulation a necessity. The construction of physical prototypes and long design cycles are undesirable, and hence, rigorous, accurate, and fast simulation of packages is required.
Via structures are predominantly used in multilayered packages and printed circuit boards to connect together traces residing in/on different layers. These packages typically include at least two separated conducting planes that are metallic, and multiple vias extending between the two or more planes for connecting signal traces disposed on the different planes. These packages are used extensively, primarily because of high speed, high densities, and routing complexity. From electromagnetic theory, voltages at the active via ports are represented as magnetic ring current sources, which in turn generate electromagnetic modes inside the plane structure. Substantial electromagnetic coupling occurs, even in well separated vias. The electromagnetic modes propagate along the plane structure and are scattered by other cylindrical vias, induce voltages at idle ports and currents on idle vias, and in turn, affect the active signal-carrying via. Such parallel plate waveguide effects are induced by the multilayered geometry. As a higher order effect, the affected vias can in turn influence the original signal. Because of the waveguide modes, such coupling is not necessarily localized in space. This lack of localization poses considerable design problems, particularly at high frequencies, in achieving reliability, high speed, and in implementing a simulation. Such coupling can even cause unreliable behavior or complete signal failure, along with signal integrity loss, longer delays, and inappropriate switching of signals.
When logic gates alter their states, transient noise is generated on vias. Due to coupling between vias, spurious signals then occur throughout the multilayered structure, primarily through cylindrical wave modes coupling to parallel plate modes. If such signals reach terminal ports, the noise can affect input and output devices through spurious switching signals, thereby degrading system performance.
Several different methods have been developed to attempt to model the crosstalk or coupling mechanism through equivalent circuits. For instance, lumped inductance or capacitance models have been developed. Unfortunately, these models only function well at very low frequencies. In particular, propagation and high-frequency scattering effects are not modeled accurately with this method. Therefore, this method is not suitable for modeling high speed electronic packages.
High accuracy numerical techniques have also been developed to address this problem. The Method of Moments (MoM) is an integral equation method formulated in the frequency domain, while the finite difference time domain (FDTD) is a differential equation method formulated in the time domain. Both methods can theoretically be used to accurately solve the coupling problem. Unfortunately, these techniques require massive computational time and memory overheads and in practice, have therefore been limited to modeling only small portions of an entire electronic package. Accordingly, such techniques are impractical for modeling a complete multi-conductor, multilayered package structure. Indeed, the efficiency of these methods is dramatically worse than the efficiencies of analytic or semi-analytic approaches.
One semi-analytic approach employed to account for coupling noise between coupled vias is disclosed in “Coupled Noise Analysis for Adjacent Vias in Multilayered Digital Circuits,” by Qizheng Gu, et al., (IEEE Transactions on Circuits and Systems, Vol. 41, No. 12, December 1994). In this reference, coupling between two adjacent vias is analyzed using equivalent magnetic frill array models. These models are combined with even-odd mode decomposition. This method assumes symmetry of the two vias and neglects the influence of other vias. In reality, it is necessary to model large-scale distributed coupling effects among many vias due to large-scale mode coupling and crosstalk. Hence, this technique is not suited to use with multiple coupled vias in a multilayered environment.
Another semi-analytic approach is employed in the Speed2000 modeling application developed by SIGRITY Inc., of Santa Clara, Calif. The Speed2000 modeling application employs an impedance transformation technique. The technique assumes that the package has an inherent input impedance associated with a via that is essentially dependent upon the radius of the via. A numerical model is created for a portion of the physical electronic packaging structure containing the via. The effective input impedance of the numerical model is then determined and transformed to essentially match the input impedance of the physical structure. A time domain technique is subsequently used for the propagation problem. This method, although fast, may provide results having excessive errors. Errors arise because the input impedance of a via is dependent not only on the radius of the via, but also on the radius of the anti-pad, and because the effective impedance can only model the via inside the numerical model and its first order interaction with other portion of the physical structure, but may not account for the multiple scattering effect of all the vias inside the physical structure.
It would therefore be desirable to develop an electronic package modeling technique that can accurately model multiple coupled vias in a multilayered environment. Such a technique should account for the multiple scattering effect of all the vias inside the physical structure, as well as accurately modeling both interior and exterior conditions.